Typically, most of the power consumed by a graphics processor (“GPU”) while it renders video data for display is consumed as a result of the toggling of clocks within the GPU.
Conventional methods for power management of processing circuitry (e.g., CPUs and graphics processing circuitry) include placing the processing circuitry in a state in which it consumes low power when it is idle, placing a circuit block of the processing circuitry in a state in which it consumes low power when it is idle, and controlling at least one voltage asserted to the processing circuitry and the frequency of at least one clock used by the processing circuitry to reduce power consumption.
Each of the following terms is used throughout the specification, including in the claims, in the following sense:
“system” denotes a computer system, for example a desktop, laptop, or handheld computer, that connects to a host slave unit (defined below) of a device (defined below). A system typically comprises at least a CPU, a GPU, a memory, at least one input device, and a display device (e.g., a liquid crystal display or other flat panel display, or cathode ray tube monitor);
“device” denotes a graphics processor chip (or a graphics processing portion of a chip, sometimes referred to as a graphics “core” or “core portion”) that includes a host slave unit (defined below) and at least one subsystem (defined below) configured to be connected to a system through the host slave unit. A device also includes one or more device clocks (defined below), one or more subsystem clocks (defined below), and a host clock (defined below);
“subsystem” denotes a block of logic, the registers for which are physically related by a common subsystem clock (defined below);
“host slave unit” denotes a block of logic that responds to slave accesses to a device that are initiated by a system. A PCI slave interface implementation is an example of a host slave unit;
“system bus” denotes an interconnect between a device and other elements of a system that includes the device. An AGP bus is an example of a system bus;
“host control bus” denotes an interconnect (within a device) between the host slave unit and each subsystem of the device. The device employs this interconnect to respond to host slave unit accesses directed towards a subsystem;
“host register” denotes any register accessible via a host control bus. For example, a status register that can be read by system software to determine the state of a subsystem is a host register. To avoid system hangs inadvertently caused by system software, host registers must always be responsive to host accesses;
“non-host register” denotes any register other than a host register. For example, the pipeline registers in the data-path of a typical device, and the state registers in a typical state machine of a device, are generally non-host registers;
“subsystem power management” denotes the discipline of managing power within an individual subsystem of a device;
“device power management” denotes the discipline of managing power globally across a device, rather than at the individual subsystem level;
“peak power management” denotes the discipline of managing the peak power of a device so as to reduce its thermal design point (defined below) to match system design limitations;
“thermal design point” denotes the maximum allowable power dissipation for a device. It is a parameter used by system designers to determine strategies for removing heat;
“device clock” denotes a device-level clock generated by circuitry (e.g., a PLL) internal to a device, or a device-level clock generated externally to a device and asserted to a pin of the device. In preferred embodiments of the invention, each device clock of a device is responsive to device clock controls described herein;
“host clock” denotes the clock that controls a host slave unit. In preferred embodiments of the invention, each host clock of a device is responsive to host clock controls described herein; and
“subsystem clock” denotes a separately controllable branch of a device clock that terminates at a subsystem. Circuitry of the subsystem operates in response to the subsystem clock. In preferred embodiments of the invention, each subsystem clock of a device is responsive to subsystem clock controls described herein.